The present invention relates to a semiconductor memory device in which DRAM (Dynamic Random Access Memory) cells are integrated and arranged and particularly to a layout system of a DRAM core circuit.
Memory cells constituting a DRAM are constructed in a relatively simple structure, and therefore, a DRAM is the most highly integrated device among MOS-type semiconductor memory devices. At present, mass-production of 64M-bit DRAMs has been started and prototypes of 1G-bit DRAMs have been announced.
An integration of DRAMs has proceeded more and more highly, and the processing speed of DRAMs has been improved. However, since the processing speed of DRAMs cannot match up to surprising improvements of the processing speed of CPUs, total performance of a computer system depends on the processing speed of DRAMs, in recent years.
In order to solve the above-mentioned problem, a high-speed cache memory is provided between a CPU and a DRAM. The total performance of a computer system is improved by making a CPU access data through a high-speed cache memory.
In this kind of computer system, a DRAM must fill a cache line of a cache memory at a high speed. It is therefore more significant for a DRAM to make serial access than to make random access. As a result, an operation mode for burst-transferring data at a speed as high as possible has become the main trend in the field of general purpose DRAMs. For example, at present, DRAMs of an EDO (Extended Data Out) mode are more often used than DRAMs of a FPM (Fast Page Mode). In the future, the main trends of main memories will surely be a synchronous DRAM (SDRAM) or a Rambus DRAM (RDRAM) which can make access at a high speed in synchronization with an external clock.
Meanwhile, there is a case that a multi-CPU having a plurality of CPUs is used to further raise the performance of a computer system. This multi-CPU system is presently adopted only in a high-performance server machine. However, the multi-CPU system is expected to be adopted in a consumer multimedia system used mainly for real-time reproduction of movies. In this multi-CPU system, random access is as significant as serial access. This means that a memory element having a very high data throughput is required.
In response to this requirement, consideration has been taken into a system in which a large capacity DRAM is divided into a plurality of blocks (or banks) and the blocks are operated independently of each other. The system is generally called an interleave system. With use of the interleave system, it is possible to improve the throughput of data during random access so that validity of a data bus between a CPU and a DRAM can be raised and performance of the system can be improved. For example, Jei-Hwan Yoo et al. reported a 1G bit DRAM having 32 banks (in "A 32-bank 1 Gb Self-Strobing Synchronous DRAM with 1 Gbyte/s Bandwidth", IEEE Journal of Solid-State Circuit, Vol. 31, No. 11, Nov., 1996, pp 1635-1644).
The following explains a bank structure method called a merged bank architecture reported by Jei-Hwan Yoo et al.
FIG. 1A shows a conventional DRAM. In the following, the same components are denoted by the same reference symbols and explanation thereof will be omitted herefrom.
Each of memory banks BANK0L to BANK7L has a memory capacity of 16M bits. A row decoder X-D and a column decoder Y-DEC are provided for each of the memory banks BANK0L to BANK7L.
In the conventional method described above, memory banks are operated independently of each other, so that a row decoder X-D and a column decoder Y-DEC are required for every bank. Therefore, there is a problem that the chip size is increased if a multi-bank system is adopted.
In order to avoid an increase of the chip size, adjacent banks may use a data bus and a row decoder in common. In this case, however, adjacent banks cannot be operated independently of each other and the number of valid banks is decreased. As a result, the data throughput of a DRAM is lowered and the performance of a computer system is lowered.
FIG. 1B shows a bank structure method called a merged bank architecture considered by Jei-Hwan Yoo et al.
In this structure method, a column decoder Y-DEC is provided at a lower portion of a chip and is shared by memory banks BANK0L to BANK7L.
Also, a data line GIO is shared by different banks. The data line GIO is provided so as to penetrate memory cell arrays on memory cell arrays.
In this method, a column decoder Y-DEC and a data line GIO are thus shared by a plurality of memory banks, and the chip size can therefore be reduced to 85.5% compared with a conventional method shown in FIG. 1A.
FIG. 2A shows a specific circuit example of a merged bank architecture shown in FIG. 1B.
In each of the memory banks BANK0L to BANK7L, memory cell arrays each having a capacity of 256 Kb are arranged in an array of (4 longitudinal pieces).times.(16 lateral pieces). Sense amplifiers S/A are provided at upper and lower portions of each cell array. The sense amplifiers S/A are connected to first data lines LIO extending in the lateral direction.
Second data lines GIO extend in the longitudinal direction, crossing memory banks BANK0L to BANK7L. The first lines LIO and second data lines GIO are connected through multiplexers R/W MUX.
Local column decoders LCD are respectively provided for memory banks. FIG. 2B shows a circuit example of a local column decoder LCD. A global column select line GCSL extends in the longitudinal direction, crossing memory banks BANK0L to BANK7L, and an end of the line is connected to an output terminal of a column decoder Y-DEC. A signal BANKCAi is used for activating an i-th memory BANKiL, and a signal BANKCAiB is an inverted signal of the signal BANKCAi. A local column select line LCSL extends in the longitudinal direction in a memory bank. In a local column decoder LCD of a bank activated, when the signal BNKCAi rises to a high level and the signal BANKCAiB goes to a low level, a transistor T1 is turned on and a transistor T2 is turned off, so that a global column select line is electrically connected with the local column select line of the bank.
Data from a memory cell is transferred through a first data line LIO to a second data line GIO when a signal on a local column select line rises to a high level.
The bank structure method shown in FIG. 2A has a following problem.
In this circuit, a column decoders Y-DEC is shared by different banks and a second data line GIO is also shared by different banks in order to reduce the chip size. Meanwhile, in order to operate banks independently of each other, a local column decoder LCD is required for every bank.
Thus, regardless of column decoders Y-DEC are shared, every bank requires a local column decoder LCD so that the chip size cannot be greatly reduced.
FIG. 3 shows a circuit example without use of a local column decoder LCD. FIG. 3 shows a memory cell array 1, a sense amplifier 2, and a selection switch 3. Two transfer gates 4 and 5 connected in series and two transfer gates 6 and 7 connected in series are respectively provided between a bit line and a first data line LIO or bLIO. The gates of the transfer gates 4 and 6 are supplied with a bank activation signal CAi and the gates of the transfer gates 5 and 7 are supplied with an output signal CSL from a column decoder Y-DEC.
However, in the circuit shown in FIG. 3, the number of transfer gates is greater than in the circuit shown in FIGS. 2A and 2B. Therefore, the operation speed is lowered as the chip area increases.
Also, in the systems shown in FIGS. 2A to 3, it is necessary to take into consideration a case that adjacent banks are simultaneously activated, and therefore, it is not possible to adopt a shared sense amplifier system in which sense amplifiers are shared by adjacent banks.
The shared sense amplifier system will be explained with reference to FIG. 4. A sense amplifier 10 is shared by memory cell arrays 8 and 12. A selection switch 9 is provided between the memory cell arrays 8 and 10, and a selection switch 11 is provided between memory cell arrays 12 and the sense amplifier 10. The selection switches 9 and 11 are respectively turned on when the memory cell arrays 8 and 12 are activated, and are respectively turned off except when the memory cell arrays 8 and 12 are activated. Turning on/off of the selection switches 9 and 11 is performed in accordance with an address signal, for example.
By thus using the shared sense amplifier system, a sense amplifier section is shared by two adjacent memory cell arrays so that the chip size is reduced greatly.
As has been described above, according to the systems reported by Jei-Hwan Yoo et al., a local column decoder LCD is provided at an area between memory banks and it is required to take into consideration a case that adjacent banks are activated simultaneously. Therefore, a shared sense amplifier system cannot be adopted in the systems. Consequently, the chip size cannot be reduced much. Particularly when the number of banks is increased, the above-mentioned problem becomes serious more.
Thus, in a conventional bank structure method, there is a problem that the chip size is increased in proportion to the number of banks when realizing a DRAM consisting of a number of banks.